At the current state of the art, processors are operating at clock rates of 1 GHz or higher, and further advances in operating rates can be anticipated. However, at current and expected future clock rates, noise generation and power consumption are significant issues in connection with clock signal distribution. For example, in one processor operating at 1 GHz, the power consumption of the clock tree accounts for about 75% of the power consumed by the chip.
Furthermore, with conventional clock distribution techniques it has been considered desirable to limit the amount of clock gating employed in processors operating at the high frequencies referred to above, since turning on and off gated clocks may result in noise spikes.
Accordingly, it would be desirable to provide clock signal distribution in a manner that accommodates very high clock frequencies with a reduced noise profile and reduced power consumption.